[boibombeiro]

Memory cells are the thing that uses the vast majority of power in a CPU. And they are used everywhere, cache, uOP cache, BTB, etc.

Async CPU solved a problem that would have marginal benefit in a metric we care about

Also, I imagine, they would need to be implemented assuming the worst timing delay from the processes. They can't be binned like modern CPUs.

[IshKebab]

That doesn't sound right? Dynamic power is consumed by toggling wires, and memory cells are going to be one of the places where toggling is rare because you can't access all memory all the time.

Am I missing something?

[boibombeiro]

The comparison of power usage is often done in the context of external memory. When talking about in-chip memory it becames an apples to orange comparison.

For start, it doesn't make sense to power gate a SRAM. So they are always leaking power. And despite writes not being common, reads are. Most application with SRAM reads all the metadata in parallel looking for a match (and often the data too due timing constraints and increased size of control logic because the extra complexity). And reading uses power.

[hypertele-Xii]

Volatile memory consumes constant power to remember its value. Processing circuits only consume power when activated. And it's difficult to get the memory bandwidth saturated in a way that keeps all circuits busy. Computers do work in bursts; Then they wait for data. And practically all classical computer science data structures trash cache, like linked lists and OOP in general.

[Taniwha]

You're confusing DRAM and CPUs - CPUs almost only use static SRAM cells internally which don't require refresh

[hypertele-Xii]

Wikipedia says "SRAM is volatile memory; data is lost when power is removed."

So it must consume power to retain its value.