[gnull]

Clash is not pseudo, it's actual HDL. Right now it compiles to Verilog, yes, but this is minor a technicality.

> the choice of HDL (which was 95% of the time, Verilog, for the rest, VHDL), was never actually 'important'; the language features were never critical to the completion of the project

Because both are equally bad, and have little meaningful difference in their features.

> Verilog is fully adequate for any kind of serious HDL development.

This confirms my past experience of interacting with hardware people. They have extremely low standard for their programming languages and tooling in general, and don't like reflecting on these too much. They just suck it up and do the job, no matter what.

My Verilog just quietly accepts the code which assigns values to a wire which is declared as input? I guess it's my fault, I will just be more careful in the future not to do that again.

My Verilog doesn't allow parametrizing modules with anything other than natural numbers? Well, I'll just duplicate code, that's how we always did it.

My Verilog has no types other than "wire" and "array of wires" (and also allows assigning array[2][3] to array[3][2] emitting no warning)? It's fine, I will just try to keep in mind what data I have in which wires and try to make sure I never mix things up.

My Verilog uses pseudo-imperative code with "assignments" in it to describe a network of flipflops with combinational logic between them? It's ok, I will just train my brain to convert between the two even though there's no good reason for Verilog to be like that.

My Verilog has constructions which are synthesizable only when used in one very specific way, instead of clearly differentiating between synthesizable (actual hardware) and un-synthesizable (imperative testing code)? It's ok, I will just remember the details.

My Verilog produces so much noise in the build logs that nobody actually reads it unless something breaks? I guess I just have to be more careful or write more testbenches.

> I just can not see how these new languages can be a serious alternative to Verilog/VHDL

This is learned helplessness.

Clash has better, more natural abstractions for the wires and flipflops. Combinational and sequential logic are clearly separated. It also uses many primitives of Haskell which make your code more compact, easier to read and verify. You can parameterize modules with anything, including other modules, this drastically reduces code duplication and lets you manage the code on a higher level (while still seeing how does it correspond to bits and wires).

[Taniwha]

As the GP points out the problem you're up against is the tooling - to be mainstream a new language needs to be supported by the main commercial ASIC tool chains - synopsys/cadence/etc, the tools from each of the FPGA, as well at least one high performance compiled simulator (probably running on both linux and windows) - then you need coverage tools, linters or equivalents, plus you need to be able to access IP libraries in all the tapeout synthesis targets (which probably means mix and match with existing verilog and vhdl libraries and IP generators).

It's not impossible, but it is an incredibly big chicken and egg problem where most of the pieces are out of your control - the best you can do is to make highly efficient (ie synthesises well, simulates well) verilog or vhdl and hope enough people start using your tooling that the big vendors choose to implement your language as a target.

(oh and My (system)Verilog has far more types than just wire, is accepted by the big guy's tooling and generate allows me to avoid almost all copying)

[gnull]

I'm trying to look at one specific component here, the language itself. My claim is that as a language Clash is way better than SystemVerilog.

True, Verilog has more mature tooling and is better supported by vendors at the moment. But most of it is because Verilog is old, and because hardware people have little knowledge of (and demand for) good programming languages; not because it's a good language (maybe it's better than the other even worse languages, but it's not good by the software programming standards). It's not that Verilog is somehow inherently good for implementing tooling for it, absolutely not better than Clash.

> far more types than just wire

You mean integers and C-style structs? “Far more” is a big stretch here. And these “types” are not very useful: they are only used to decide how operators should behave on values. As far as I remember, even Verilog's assignment doesn't care about types, as long as left- and right-hand side have the same number of bits, the assignment is allowed.

> generate allows me to avoid almost all copying

At the cost of: extra work (you're essentially implementing polymorphism by hand), inferior readability, increased risk of making mistakes, no support from the compiler. Generate can be almost perfectly replaced by code generation in Python.

Seriously, look at the way Clash allows parametrizing things, you will be impressed.

[laydn]

It's not that we have a low standard, it's that we are bound by the full suite of tools that are provided to us in order to achieve our design objective.

When I am close to tapeout and I am moving a single gate across a flip flop in order to extract the final few Mhz out of the design, and my formal equivalence checker only understands Verilog, I will have to use Verilog.

I suppose my benchmark in assessing the capabilities of this -or any- language and its ecosystem is the following : Can you use Clash in the design of a reasonably complex chip from scratch (HDL to tapeout)?

[typon]

Software people also have deadlines, less strict than hardware sometimes, but they still do. If people in Silicon Valley thought the same way as hardware folks, we would be using Java for all applications and Oracle databases. But instead we have a huge ecosystem of open source databases to choose from and and a plethora of languages designed for different tasks.

I worked at Intel designing tools for hardware people to use (I am also a hardware person, but I see the power of software) and it was years of hair pulling to get anywhere, even in the face of clear advantages being offered.

Why isn't there an open source simulator as powerful as vcs out there? Why don't we have open source timing analysis tools? Because the culture just doesn't encourage exploration in these areas. And if you try, people will just not take you seriously.

[gnull]

I don't know what is tapeout, but Clash can describe any circuit that Verilog can. If you wanted to, you could one-to-one translate the circuit descriptions between the two.

We could argue about the current state of tooling for Clash and its ability to work together with vendor-specific tools and other ecosystem stuff, I don't know much about this. But as a language Clash can do everything Verilog does.

[tubby12345]

>I don't know what is tapeout

The person you're responding to isn't an FPGA dev (or at least not primarily). They're talking about verilog for ASIC design where the last step is is making the lithography mask that "tapes off" parts of the silicon substrate (like a painter tapes parts of a wall when painting).

I play in the space (Chisel and FIRRTL and CIRCT) so I agree with you but you're being far too dismissive of the people you're aiming to convert.

>But as a language Clash can do everything Verilog does.

Ironic since people say the exact same thing of Haskell and eg python and yet we still don't have wide Haskell adoption.

You have to deeply internalize that a PL or HDL is a tool. Thus, this position makes zero sense

>its ability to work together with vendor-specific tools and other ecosystem stuff, I don't know much about this

No one uses tools that don't fit somehow into their workflow. Further, if the users of the tool are happy with their current toolset then you have a very hard road to hoe in convincing them to adopt your tool.

[gnull]

Sorry it it came out as dismissive. I only wanted to show that my claim is specifically about the language, not current state of tooling which I'm not as familiar with (and which is important).