[rowanG077]

I've been using Clash for about 2 years now. I just debug the clash code. As in just use the normal Haskell test tooling. The only reason I ever read the generated HDL is when I make sure I have integrated another IP correctly.

[tubby12345]

qq: i know that for HLS sometimes (most?) the generated HDL is 10x the number of resources (flip-flops?) compared to hand-written HDL. how bad is clash in this respect?

[rowanG077]

Clash is not HLS. You have full control of register placement and pipelining just like VHDL and Verilog. Clash in that sense is not "higher level" then VHDL or Verilog. In some respects you could even say that Clash is "lower level" because you don't write things just right to be inferred correctly. You actually specify what hardware you want. E.g. you write I want a blockram with this size here, and not if I write this specific Verilog the tools will infer a blockram.

What Clash gives you is the power and tooling of Haskell.

[tubby12345]

>Clash is not HLS

i don't understand - how do you generate the bitstream if you're not generating verilog or vhdl first?

[rowanG077]

Clash does generate Verilog or VHDL but the only reason it does this is to interface with vendor tooling.

HLS generally means you compile a very high level description of computation to VHDL/Verilog. This high level description doesn't contain hardware details like registers, ram usages, pipelining etc. During the process of HLS the synthesis tool will try to translate this description to a digital circuit. It will itself place registers, rams pipeline as necessary.

That is the reason HLS doesn't reach the performance of VHDL/Verilog, these HLS tools just aren't as good as a human making the digital circuit.

Clash is not itself coming up with a digital circuit like HLS is doing. The developer is specifying the digital circuit. Just like with VHDL or Verilog. It's just an alternative way of writing it.

[tubby12345]

got it - it's like chisel. thanks

[rowanG077]

Looking at your posting history I can be a little more concrete: Chisel is essentially a metaprogramming framework for VHDL/Verilog. Clash is a compiler closely based on GHC that compiles Haskell code, not a DSL defined within Haskell, to VHDL/Verilog.

[rowanG077]

Not exactly. Chisel is a DSL while clash is not. But it's at the same level of circuit design abstraction.