[hinkley]

It sounds to me like ECC isn't being included in the DDR5 spec due to magnanimity so much as because it doesn't function without it. That ECC has become 'load-bearing'.

Does that mean we need an extended ECC to deal with critical systems that require additional robustness?

[Legion]

Who error checks the error checkers?

[RedShift1]

It's just a matter of time before someone finds a way to exploit the ECC part, calls it Hammerrow and brings us back to square one...

[aaaaaaaaaaab]

Rowhamming would be a better pun, as DDR5 uses a Hamming code for error correction.