[tlb]

DRAM cells also decay over time (~ 60 milliseconds), but memory controllers have some logic to refresh every row on a regular schedule so it's not an issue.

They should also have logic to refresh adjacent rows if some number of consecutive accesses to a small group of rows is detected. This is rare in normal workloads, because those accesses normally come from cache. It's lame of chipmakers to not fix this. The fix would requires the DRAM controller (integrated into modern CPUs) to know more about the internals of DRAMs than they currently do.

[zsmi]

In theory DDR5/LPDDR5 added a controller command for RowHammer mitigation but I haven't had time to research it yet.

See: https://arxiv.org/pdf/2108.06703.pdf