Saying that the M1's cores are homogenous is pretty misleading / confusing as the icestorm and firestorm cores are rather different. big.LITTLE/DIQ-type architectures are usually considered heterogenous even if all the actors share an ISA (because you can't treat all the cores
Yeah, when I said "homogenous" I was solely referring to the ISA. Trying to enable TSO on a Tempest core will fail with an undefined instruction exception, but I think A12Z is ISA homogenous in userspace.
But as to the latter assertion, you're indeed correct per Joe Groff (Swift compiler engineer at Apple): https://twitter.com/jckarter/status/1332045390057639939
> The A12 only supported TSO on the performance cores. The M1 supports it on all cores.