[ruslan]

I'm also confused by "larger area less capacitance" statement. Can someone please elaborate on this ? Why larger area around the gate is needed and how it lowers the parasitic capacitance which is main obstacle on the way to higher frequencies ? This looks counterintuitive.

[dragontamer]

Hmmmm. I could have sworn it was gate capacitance that the surface area is for. But you're right. I got it backwards. Capacitance grows with surface area.

I remember that surface area of the gate was __very important__, and is the key driver of all of these new and interesting shapes we're seeing. But I seem to have err'd on the reasoning behind that.

baybal2's point about the "strength of the field" seems to be correct. That would mean that surface area would cause the field-effect to turn on faster / stronger?? (aka: lower Ohms / resistance when on, and less energy to reach the on-state)

Well... that's if I'm remembering the physics correctly this time, lol.

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EDIT: A FET (field-effect transistor) is the type used in CMOS arrangements. Most people will use BJTs in their undergrad studies, with maybe some FETs.

FET has a gate, source, and drain. The "gate" turns on the source->drain in nMOS (or drain->source in the case of pMOS). The more voltage you put on the gate, the lower the resistance of the source/drain gets.

Its called the "field effect" because the electrical field on the gate (caused by literally shoving electrons into that location), causes a negative-charge to radiate out from the gate. This charge then allows the source/drain (two pins that are nearby) to go from high-resistance (aka: 10kOhms or something) to low-resistance (maybe 0.1 Ohms).

The assertion by bybal2 is that the surface area at the gate is more about the field effect rather than capacitance. Which is... probably correct.

[ruslan]

Now it makes sense. Thank you!