|
|
|
|
|
by brucehoult
1704 days ago
|
|
When you have the complete verilog source code for the CPU core it's pretty hard to hide anything. Following the source code for the C910 core upload 24 hours ago, Olof Kindgren is live-tweeting getting it going in an FPGA using the existing FuseSoC framework. He made significant progress in the first session before going to bed. It would not surprise me if it's working in the next 24 hours. |
|
That's a big "when". The road from an ISA to a core is long, and unless the core is copylefted (this isn't), then you aren't going to get the source code for something someone else manufactured either.