[beefok]

Hm, every vendor with free tools (Xilinx/Altera/Lattice/Microsemi etc), seem to be fine with it, along with the usual vendor-specific Modelsim. In fact, most "verilog" synthesis tools actually synthesize SystemVerilog. Out of curiosity what tool are you referring to?

Thanks!

[mhh__]

There isn't much support if any in open source tools, if free means free software.

[gchadwick]

There's few open source tools for any HDL full stop.

Indeed I'd say SystemVerilog is doing better on that front, as Verilator (https://www.veripool.org/verilator/) supports SystemVerilog and is probably the best open source tool for 'real' HDL work (note the number of industrial users).

[beefok]

I didn't mean open source, no, and it looks like the free version of yosys has limited support of systemverilog.

What I meant were the free toolchains provided by all of the FPGA vendors. They typically support SystemVerilog in synthesis and modelsim as far as I have seen.