Verilator can simulator a subset of SystemVerilog, mostly that which is synthesizable (though work is on-going to expand its capabilities so it can run UVM code).
So it's a replacement for modelsim if you're just using it to run your actual design RTL. You need to build a synthesisable testbench or write one in C++ (or check cocotb: https://github.com/cocotb/cocotb)
Verilator can simulator a subset of SystemVerilog, mostly that which is synthesizable (though work is on-going to expand its capabilities so it can run UVM code).
So it's a replacement for modelsim if you're just using it to run your actual design RTL. You need to build a synthesisable testbench or write one in C++ (or check cocotb: https://github.com/cocotb/cocotb)