[cushychicken]

Thanks for the detailed answer! I feel like my college HDL course was better than most given that they did give us exposure to wiring up FSMs together. (Not that I remember any of it.)

if anyone wants to create a HDL without the crippling expressiveness flaws of either VHDL or verilog, I will personally transmute myself into a solid gold toilet especially for them

If I ever do this, and get rich off of it, count on me to seed fund your personal transformation XD