[skissane]

If we are just looking at the fabrication process, as opposed to CPU architecture, MTr/mm² – million transistors per a square millimetre. But transistor density can be variable depending on the type of circuit, so the standard calculation uses a weighted average of two different cell types – NAND2 and SFF (scan flip-flop)

https://en.wikichip.org/wiki/mtr-mm%C2%B2

[perl4ever]

A while ago, I just tried taking any figure I could find for transistors per area, for various processes/chips, ignoring all the nuances, and taking the square root to get the implied linear density, and if I recall correctly, it was pretty consistently 1/10th of the usually quoted figure.

Whatever the ratio was, it seemed to be roughly consistent going back like 30 years, which surprised me.

So now I don't believe there actually has been a drift towards marketing and inaccuracy. And believe the details of what kind of cells is just excessive precision.

[monocasa]

If you were comparing it to the Nnm figures, that actually checks out and is higher than I thought it would be. Nnm has been "feature size" not transistor size for eons now. It's the size of the smallest single shape the process node can do. So, like the width of a corner of a fin on a finfet.