There are a few comments saying that 3nm is a marketing term and that the transistors are actually larger - how is this allowed? Isn't it misleading and deceptive?
Well, I hope nobody chooses a fab based on the headline number on their marketing material. Adapting your design to them is a long process that requires all kinds of details, and how well they will produce your circuit depends on those details as much as on the feature size.
There are no features with lengths of 3 nm, 7 nm etc.
Some vertical distances, e.g. thicknesses, are indeed of only a few nm, but the process size name always referred strictly to horizontal distances (i.e. parallel with the wafer surface), which are determined by lithography. Those are at least 10 times larger, in the range 25 nm to 60 nm for modern processes.
There are a few horizontal distances that are not determined by lithography, i.e. they do not correspond with something drawn on the mask, but the distances are determined by speeds of corrosion or diffusion, like also for the vertical dimensions, but those also do not count for naming processes, because you could have such a distance of only e.g. 5 nm even in an 180 nm process. Those distances that are not determined by lithography do not influence the potential density of a circuit but only certain electrical performances.
3 nm is not the size of these transistors, just like X nm has never been the size of transistors for any value of X, so it's not "misleading and deceptive".
Actually it is all about marketing now, the customers though to whom they market are MNCs with immense cash piles to splurge on microchips. Nobody else can.
See — you rarely ever see so much marketing money spent on an industrial service, and like here seeing Hollywood level gfx on an obscure industry event keynote would've been more laughable than noteworthy 10 years ago.
Without these cash piles, there is no way to finance new fabs, and SEL is fighting for its survival here. Once you are out of the race in semi industry, you can never catch up.