[_chris_]

> They said "5 stage", which sounds to me like no out-of-order fancy stuff of the sort we've been used to.

That's inefficient for an FPGA softcore; wires are too expensive, CAMs are straight up awful, and memory latencies aren't too far off relative to the core clock frequencies to justify OOO stuff in the normal case.

> Well, I wrote a little 5 stage CPU FPGA program once (In Haskell compiled to Verilog :), but that's another story). It wasn't very hard.

Writing a 5 stage is easy.

Writing a 5 stage with no bugs is much harder.

Writing a 5 stage that talks industry standard busses and provides Debug/JTAG Support at high frequency and small gate counts is, well, an actual job.

Not saying you can't do better, but it's not a trivial effort.