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by bananaportfolio
1727 days ago
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It looks like they were able to exploit the Last Level Cache of Intel and Apple processors, but failed to do so against an AMD processor using the Zen architecture. Instead of plainly saying as much, the authors simulate a theoretical leakage rate for AMD processors by way of making V8 expose clflush in absence of a practical LLC eviction mechanism. |
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AMD introduced the Clflush instruction which was supposed to decrease the number of TLB misses and improve performance. This instruction was ultimately responsible for making V8’s behavior erratic and unpredictable with regards to memory operations.
Modern processors with x86-64 architecture support 2-way page tables and most modern operating systems support several layers of virtual memory. However, many of these techniques made the V8's behavior unreliable and unpredictable which led to a performance hit for AMD processors with AMD chips especially those who implemented TLB remapping instructions.