[ausbin]

This extension is great. If anyone is interested, my roommate and I partially implemented the previous revision of it on a RISC-V GPU called Vortex: https://carrv.github.io/2021/papers/CARRV2021_paper_87_Adams...

I'm excited to see that the RV32 AES instructions now have separate rs1 and rd fields, because the previous version combined them into just rt, which was kind of annoying from an implementation perspective, since you had some register that was both input and output (iirc, unlike any other RV32 instruction previously implemented on that hardware)

[Narishma]

It is correct to call Vortex a GPU? I looked at the github but there doesn't seem to be anything there related to graphics.

[spijdar]

It appears to target "GPGPU" APIs like OpenCL and CUDA via translation, making it more like Xeon Phi in that its architecture and instruction set is vaguely GPU-like, while it lacks video output or fixed-function pipeline hardware for graphics stuff.

Also like Xeon Phi, I'm guessing you could add that hardware, it just hasn't been done because the other priorities were more interesting, and the practical performance would be "disappointing".