The entire EDA stack from front to back is so ridiculously bad. System Verilog, UVM and the ecosystem that works on it are equally terrible. Just depressing all around.
Once we have a high quality "LLVM of digital logic", we have a great foundation for better high-level tools. It's just a matter of funding and motivation. In my dreams some Chinese FPGA upstart decides to invest huge in the open tools rather than negotiate with the current toolchain vendors...
Have you read the verilog spec? Half the commercial vendors haven’t implemented large portions of the spec or have implemented it differently from each other.
I’d love to have the momentum around open source EDA tools. At this point I’m not hopeful though.