[jgab]

One aspect is meeting the overlay and CD targets throughout the stack to meet yield. Having a process that can find defects and more importantly practices to minimize the defects in your process is a big piece. Typically the process given to mass production would be only half solved and then the fab is trying to refine it in ramp.

I used to manage a fab of high end ASML tools and there is a non trivial list of things to continue and solve. You have reliability issues that require scheduling long (2-5 weeks) downtime to fix.

An upstream defectively issue in a spinner tool might lead to taking one dispense or develop node out of flow to improve the defect rate but in turn tank the Scanner efficiency by 40% as it waits to output wafers and that backs up the imaging. The reality is the ASML tools given to fans don’t have everything ironed out at rhe start. So fabs see the reliability issues in real time but there’s no time for the fab to take it out of production for 3 months to address a major part replacement. These all lead managers to make bad choices that continue to dig you in a hole.

At the time I was supporting 14nm it was well known TSMC had world class software tools and practices to minimize their fabs defects and maximize higher order control of overlay and CD bias. This allows them greater flexibility to take a tool down and fix the issues rather than live with them or have to use a band aid.

EdiT: I did not work at intel so can only speculate why they are behind but it was also well known TSMC photo engineers were worked 80+ hrs/week always . They were paid less so they hired more of them and they worked a lot longer so as a result they had better fab processes and support tools.

[dataflow]

Thank you!