[anon_tor_12345]

you don't need vivado to modify the hdl, you need vivado (or some other proprietary xilinx toolchain) to produce the bitstream which actually deploys to the fpga.

[LeifCarrotson]

That's a level of nitpicking that I didn't bother with.

Of course the Verilog or VHDL is just plaintext, which you can modify anywhere, but to actually do anything with it you need to compile it into a bitstream.

It does make me wonder if someone could set up a CI server to get around proprietary compilers like Vivado. Point the community resource at your source and get back a binary! Obviously you'd need to strip the license ID...

[anon_tor_12345]

i didn't mean to nitpick and it's not nitpicky since there are now open toolchains (though not for xilinx) that you support verilog as a frontend

http://www.clifford.at/yosys/ http://www.clifford.at/icestorm/