| you'll be fascinated to know that we picked a python-based (Object-Orientated) HDL - nmigen - for exactly this reason. we've developed a dynamically SIMD-partitionable-maskable set of "base primitives" for example, so you set a "mask" and it automatically subdivides the 64-bit adder into two halves. but we didn't leave it there, we did shift, multiply, less-than, greater-than - everything. https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/iee...
https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/iee... can you imagine doing that in VHDL or Verilog? tens of engineers needed, or some sort of macro-auto-generated code (treating VHDL / Verilog as a machine-code compiler target). the reason for doing this - planning it well in advance - is because we're doing Cray-style Vectors (Draft SVP64) with polymorphic element-width over-rides. yes, really. the "base" operation is 64-bit, but you can over-ride the source and destination operation width. the reason why we're using our own Cell Library is actually down to transparency. we want customers to be able to compile the GDS-II files themselves, fully automated, no involvement from us, no manual intervention. ironically, as an aside: Staf's Cells are 30% smaller (by area) than the Foundry equivalents. |