[rkangel]

> Networking has legacy reasons from the bad old days when byte order wars were still a thing, but those days are gone.

Yeah, this isn't true. Low level hardware receiving data still likes to use shift registers:

    * Zero shift reg
    * clock in one byte, shift into shift register
    * Clock in next byte, shift into shift register shifting the previous byte left one
    * Repeat for as many bytes as you have

If you want this to work for a variable number of bytes, then you need most significant byte first, so that everything more significant is pre-zeroed. This is not theoretical - we did this for an FPGA network offload thing last year.

Processors can't agree on endinaness, but network protocols have. "Network byte order" is a standard thing that is almost completely universal across communication protocols.

[alfalfasprout]

This kind of misses the point of his comment though. There's now tons of ASICs and FPGAs in networking gear that relies on network byte order for optimal performance. No one's advocating for changing that.

What he is saying is that for pretty much everything else (read: typical CPUs) it's all little endian now.

[krastanov]

I am out of my depth here, but I do not really understand why this matters. Could you elaborate?

Basically, I understand that shifts for incoming serial bits is very convenient. But as long as you specify the "word size" used in your local memory, I do not see the problem: just use 8 (for instance) shifts for your 8-bit word and then go to the next memory location. Why is this fantasy wrong?