[Rochus]

Meanwhile there are surprisingly many programming languages with a "synthesizable subset" meant to "replace Verilog". From my point of view it would make more sense to look for a dedicated language, which does not have the uncertainty of synthesizability (because the language was originally intended for something completely different), and which does not aim at the most general case of digital design, but e.g. only RTL and behavioral level for synchronous circuits. This might be an example: https://people.inf.ethz.ch/wirth/Lola/index.html.

[ekiwi]

Chisel imho solves the "synthesizable subset" problem quite elegantly: All Chisel constructs are simple, synthesizable circuit elements and boolean functions (+ functions on fixed size integers that can be converted into boolean functions). All automation happens in the meta-language which in this case is Scala. Chisel was always intended for synthesizable hardware!

[Rochus]

Scala is a general purpose programming language. Chisel is therefore it's "synthesizable subset". To use Chisel you need to know Scala as well as the HW design specific constructs Chisel offers.

EDIT: and Scala or the functional programming paradigm are not something design or verifications engineers are usually familiar with, which was apparently also a major issue in the Google project according to the referenced talk (quote: "frankly, most hardware engineers don't really get passed this yellow [Chisel learning] curve")

[ekiwi]

> Chisel is therefore it's "synthesizable subset".

Chisel is not synthesizing Scala. It is just a library implemented in Scala that allows you to create a data structure that describes a circuit.

Something like:

  circuit = Circuit("test")
  module = circuit.module("test")
  in0 = module.input("in0")
  // ...

The one thing Chisel adds on top of an Object hierarchy that describes a circuit is what PL people normally call "syntactic sugar". I.e., Chisel makes constructing this circuit object look more like a Verilog circuit by taking advantage of some nice Scala features. However, in the background, we are just constructing a data structure that represents a circuit, just like in a GUI library you might construct a data structure that describes your widget hierarchy. Chisel is not High Level Synthesis.

[Rochus]

> Chisel is not synthesizing Scala

Obviously I neither wrote nor meant that.

[monocasa]

What I think the other user is getting at is that Chisel isn't a "synthesizable subset" of Scala. You can use any Scala you want as Chisel is just a library. The model isn't a subset of Scala that can be turned into a netlist with the right compiler, but of a library for metaprogramming netlist graphs.