[minipci1321]

Somehow I doubt this wide-sweeping affirmation, are you sure? Atom is really big family by now, starting from Silvermont it vent full out of order with all bells and whistles, I find it hard to believe OO backend is anywhere near the size of x86 insn decoder.

[rbanffy]

A complicated ISA like the x86, with layer upon layer of additions, costs a lot of silicon that will need power to run.

[minipci1321]

Let's go see some figures!

"Empirical Study of Power Consumption of x86-64 Instruction Decoder"

https://www.usenix.org/system/files/conference/cooldc16/cool...

From the conclusion:

"The result demonstrates that the decoders consume between 3% and 10% of the total processor package power in our benchmarks. The power consumed by the decoders is small compared with other components such as the L2 cache, which consumed 22% of package power in benchmark #1. We conclude that switching to a different instruction set would save only a small amount of power since the instruction decoder cannot be eliminated completely in modern processors."

[baybal2]

1. They are physically huge, and that means more leakage, when there could be none.

2. Inefficient front-end taking toll on everything behind it contributes to the rest of the chip doing nothing except dissipating power.

3. While cores on modern SoCs take much less space than everything else usually, front-ends still eat into the die area.

4. Front-end dictates how the rest of the core behind it is designed. I believe that X86 technical debt absolutely must exert its toll on that, and overall transistor count in the back-end.

[zsmi]

It's big, but not overwhelmingly so. To eye is looks like it's about 10% of the area so it jives with the quote provided by minipci1321 which claims ~10% of power.

Here is an annotated die shot of Zen2 that shows it. https://forums.anandtech.com/threads/annotated-hi-res-core-d...