[zsmi]

I looked over the Silice readme yesterday, and as a seasoned HDL engineer, I didn't see anything for me but I could see it's merit as a learning tool.

On HLS in general, I was a skeptic too until I read this paper. [1] I am still more a verilog and verilog-mode [2] kinda guy but I can definitely see the benefits. For me, it's hard to look at figures 5,6,7 & 8 and not be impressed. I've actually started using Chisel [3] because of that paper.

That said, it's not all unicorns and rainbows. Unfortunately dealing with back end CAD is kinda an issue because they use verilog as an intermediate language and one basically ends up with the C++ name mangling issue. Chisel is not so bad about it, but it's not great either.

[1] https://people.eecs.berkeley.edu/~magyar/documents/firrtl-ic... [2] https://veripool.org/verilog-mode/help/ [3] https://github.com/schoeberl/chisel-book