[danbst]

Wonder how Forth and Forth-chips can help here.

I imagine a tiny Forth, which interprets larger Forth, which implements C enough to compile old TinyCC/GCC and start the chain of rebuilds (as explained in stage0).

As for hardware, a schematic for Forth would be simpler than schematic for generic RAM machine. But if not, intermediate minimal RISC-style machine language is still fine.

Steps to reach that level of hardware are already describe in NandToTetris, so in the end anything capable of implementing NAND/Fanout/Wiring can be used to run bootstrap chain.

Then we only have to make sure HW and SW implementers don't introduce bugs.

[dave_universetf]

The stage0 project has a Forth implementation of the middle layers (between the pure hex writer and Mes), but according to the author Forth wasn't as easy for them as straight assembler or Scheme. They say the Forth code is sitting there, waiting for a Forth expert to come and prove them wrong. Have at it! :P