[_chris_]

> I wonder if we're ever going to see a 8wide decoder RISC-V.

Considering there are 6-wide x86 cores on the market, I wouldn't be too concerned about RISC-V going wide. The instruction length decode is a 2-bit dependency chain; whereas the renamer-dependency logic builds off of 5-bit register values, which will be the bigger bottleneck.

Note that RISC-V's compressed instructions are trivially decoded with the first 2-bits; there is no further wonkiness about needing to decode the whole instruction before you can know it's true length that can be seen in other ISAs.