[progbits]

Fully agreed. As an amateur, just trying to get into the FPGA world, my experience was very similar. I've recently discovered nMigen [1] (in a very nice series building Motorola 6800 [2]) which approaches this by using Python and overloading type operators, something like the TF dataflow model and that feels more natural.

However even for nMigen, and doubly so for Verilog/VHDL, it feels very 90s when it comes to engineering practices. The tooling is often lacking (module management, automated testing, CI and so on), cryptic acronyms are used everywhere as if each source code byte cost a LUT, you have to keep various things (eg. signal bit widths) in sync in multiple places and many more things which make C99 feel modern.

I'll have to introduce Clash, it seems like a big step in the right direction - thanks for mentioning it.

[1] https://m-labs.hk/gateware/nmigen/ [2] https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPS...