Does this mean that the compiler can embed smart hints for branch prediction directly in the bytecode, by way of setting very specific dedicated registers?
Although it says Software Assisted Branch Prediction, it's really talking about the indirect jumps used for method dispatch rather than conditional branches used for logic.
The only static indirect jump hints I'm aware of, and Intel uses this, is next instruction. Unless it's in the BTB, the default speculated indirect jump target is the next instruction. This means the programmer should make the most common target follow the indirect jump instruction itself. See Assembly/Compiler Coding Rule 50 in the Intel® 64 and IA-32 Architectures Optimization Reference Manual
Intel used to just have branch hint prefixes but they decided to ignore them on modern (from Pentium 4) models. Perhaps Apple found a corner case where it does help, it could be Intel can do some optimization that Apple cant implement due to patents, or it’s just an experiment that is destined to fail as well.