[mikewarot]

I've had a chip design bouncing around in my head since the 1980s, now I can finally get it made. Thanks so much for posting this.

The idea is simple... a grid of 4x4 LUTs, each geographic neighbor has 1 bit in, and 1 bit out, there are 16 states, each with 4 outputs.

Turns out that this route-less FPGA can do some fairly amazing things, at least in theory. Now I intend to find out.

The really old blog I had about it - https://bitgrid.blogspot.com/

[jecel]

There have been FPGAs in the past which used the logic blocks for routing, including the Xilinx 6200. I think that was also the case for the Atmel AT40K FPGAs, but could be remembering wrong.

In fact, our project for the previous Google shuttle was an FPGA-like device which also routes data using logic cells. Here is an introduction to the idea:

https://github.com/fiberhood/MorphleLogic/blob/main/README_M...

It worked in simulation and the chip is currently scheduled to be shipped to us on September 6. There were 2 or 3 projects that were more conventional FPGAs.

[mikewarot]

The Morphie blob looks like a special case of a 4x4LUT. I'd be interested to know how the chips work out.

[jecel]

There are some common features, but also differences that makes them a bit hard to compare directly.

An academic project that takes yet another approach to this design space is:

http://cba.mit.edu/projects/rala/

[mikewarot]

Unfortunately, none of the links there go to anything, unless you have a username/password to sign in.

[jecel]

Here is a link to an "open access" copy of the 2010 RALA paper:

https://dspace.mit.edu/handle/1721.1/72349