[senshu]

In the "signal-of-vectors vs vector-of-signals" comparison, "vector" refers to the Racket data type used for arrays. It should not be confused with "bit vectors", which are represented as integers (assuming that a bit can only be 0 or 1). While it is theoretically feasible, I would rather not use an array to store bits.

I think that your question assumes a model of computation similar to VHDL or Verilog. The techniques I use in Racket are similar to those used in Clash ( https://clash-lang.org/ ) In VHDL or Verilog, signals are updated in reaction to events. In Racket, I implement signals as lazy data streams: values are "pulled" from signals, which can trigger the evaluation of other signals. This is possible because I restrict my models to synchronous circuits with a single clock domain.

You can read more about it in this post: http://guillaume.baierouge.fr/2021/03/14/simulating-digital-...