[Unklejoe]

Yep.

Generally, "platform device" means that it's just a direct physical memory map. Honestly, from a driver perspective, that's sort of what you get with PCIe as well. The physical addresses is just dynamically determined during enumeration instead. Of course, there's some boilerplate core stuff to perform mappings and handle interrupts specific to PCI, but at the end of the day, you just get a memory mapped interface.

This is unlike something like USB where you need to deal with packets directly.

[CyberRabbi]

> Honestly, from a driver perspective, that's sort of what you get with PCIe as well.

Right, I was sort of alluding to that. I’m really just curious how the NVMe packets physically make their way to the SSD.

[monocasa]

A network on chip protocol. Probably something ACE5 compatible, but Apple hasn't been public about those bits AFAIK.

[CyberRabbi]

Yes. It seems there is no distinct SSD on the system. The M1 SoC seems to communicate with raw flash. I tried looking up the datasheet for the flash ICs (SDRGJHI4) to see if they would leave any clues but it’s not publicly available AFAICT. This is rather interesting that Apple has custom or semi-custom IP that manages raw flash as part of their SoC. That does seem like a natural outgrowth of shipping iPhones for so many years.

The specific logical signals between separate IPs on the SoC is slightly less interesting to me then. It’s likely something similar to ACE5, like you said, for sharing the memory bus.

[monocasa]

Ah, yeah, it's been integrated on their SoCs for quite a while. Word on the street is that it's the (internal only successor to the) Anobit IP they bought back in 2011 with an ARM core strapped to the front for the NVMe interface.