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by tediousdemise
1892 days ago
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By decapped, do you mean delidded? Theoretically it would be possible to automate this with a couple things: - USB electron microscope to image the transistor topology - CV lib to identify connections and generate corresponding Verilog code |
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My understanding is that there are people who do it often enough that it is automated in the way you describe, but you still need someone with a lot of skill to spend serious time on it. Computer vision works wonders but there are errors which must be identified and fixed.
A lot of the chips people care about are can just be done optically, no electron microscope needed.