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by oxinabox
1918 days ago
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> Your observations in V.B.4 are pretty well understood in circuit design. Indeed, I am actually surprised the paper doesn't include something like _"This is inline with the well known result for progressive sizing [cites textbook]"_.
It was my first paper, i was worse at writing things then.
:-D > One thing your analysis didn't include, which actually ends up being quite significant, is the extra capacitance caused by the wires between transistors. This changes the sizing requirements substantially. Good point. And not easy to model in a SPICE style simulator.
I guess one could maybe introduce explict capacitors and them compute capacitiances by making some assimptions about layout. |
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That is, in fact, exactly what we do! I think it would be pretty straight forward for your large buffer example - you can model it as a fixed capacitance at each output which corresponds to the routing between inverters, which would be the same for all sizes, plus some scaling capacitance that relates to the size of the transistor itself, which you already have.
The adder would be trickier, for sure. Regardless, in my experience, just adding a reasonable estimate is good enough to get you close in terms of sizing in schematics, then you fine tune the layout.