[UncleOxidant]

After playing with some of the alternative HDLs (and even trying to make my own at one point) I've come back to just coding the design in VHDL (which I prefer over Verilog/SystemVerilog, YMMV) and using cocotb (https://github.com/cocotb/cocotb) for creating testbenches. I think in a lot of cases effective use of VHDL generate statements can do a lot of the things these alternative HDLs are trying to do anyway. The alternative HDLs try to shoehorn HDL semantics (everything happens in parallel) into languages that are serial and it ends up being awkward and not any easier to read.

Get comfortable with an HDL. Use something like cocotb to generate testbenches.