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by gpanders
1933 days ago
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I want Chisel to succeed so badly. I'm so sick and tired of writing VHDL. Verilog is no better. Also it looks like LLHD is perhaps analogous to LLVM in that they offer an intermediate representation instead of providing a language that you code in yourself. Chisel also offers this via FIRRTL [1]. I can't decide whether to be excited about the fact that there are multiple ideas in this space or frustrated that these disparate teams aren't simply collaborating. [1]: https://github.com/chipsalliance/firrtl |
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