[londons_explore]

I imagine they have a basic design in verilog with various tunable parameters (memory size, clock speed, how many instructions to issue at once).

They also have a way to run that hardware in a simulator and see how quickly it could train some network.

The ML optimization problem is to come up with a bunch of constants which performs well, but also compiles into a manufacturable chip. Clearly setting the clock speed to 9999Ghz isn't that...

[winterismute]

But what I don't understand is: they claim their approch side-steps the "unfeasible" configs, which is and would be a major achievement, however I don't see how the unfeasibility is captured in their evaluation function, which measures mostly runtime and area, and none of them give negative clear negative rewards to unfeasibility since for example, as you noticed, unbuildable configs would return high runtime... Area might correlate negatively, but at that point I don't see how some methods work (eg evolutionary algorithm) and others really don't... Did you understand that part?