[cillian64]

Indeed. The best description that I’ve heard of the process is “work out the hardware you want to exist to solve the problem, and then write the HDL code which will synthesize into that hardware”. In verilog/vhdl there are a lot of ways you can write the HDL which will give correct outputs but synthesize into hardware which is garbage (too big or won’t meet timing). You have to learn the specific patterns to write which hint to the synthesis tool what you would like it to synthesize.