[sfrigon]

Right, but I didn't mean for this specific device. I meant for higher end SoCs, as in the RaspberryPi4/BeagleBone Black or even higher end SoCs. The RP2040 could be used as an inspiration to provide the same level of freedom to other SoCs.

[dragontamer]

My overall point is that GHz-speed decoding in a flexible manner seems... difficult... to say the least.

Your discussion point of "here's a VHDL block" seems to understand the general issue. You need a non-trivial amount of FPGA-magic (LUTs) to implement logic and routing at those speeds. SATA has some kind of error-correction code if I remember correctly... so its not exactly easy to parse those messages.

[sfrigon]

I absolutely agree that this would be non-trivial and a lot of magic is required to make it happen. But it would need to be done only once, after that it can be shared to all the users, a little bit like a GPU firmware/driver.

I am just surprised that this is not more widespread among major players as a way to reduce costs and increase flexibility. Though I'm pretty sure I'm overlooking the core of the issue here haha

[mbreese]

I think one major factor is that it would increase unit costs in many cases. We are talking cheap chips that are sold in high volume. So any small increase in cost gets multiplied quickly. Combine that with competition (your competitor provides a less flexible chip, but it is $0.20 cheaper and has the IO ports you need), and you can see why we have the mess we do.

I think I’m many cases the flexibility is great during the prototype phase. But those are used at lower volume. When you move to production, you’d want to have the cheapest BOM as possible.

[sfrigon]

Well actually, it would be nice to replace any specific interface with a generic FPGA-like interface. But of course what you can implement with it would be limited to the speed of the CPU / peripheral.