[ajanicij]

I see so many comments here about RISC-V fragmentation. This is not my expertise, so correct me if I am wrong, but if this means that the particular RISC-V CPU has to be able to execute some instruction, from what I understand the RISC-V designers expect to happen is missing instructions will be implemented in software.

So if the CPU runs into an instruction that it doesn't understand, this will trigger a missing instruction trap and software can implement the instruction. Fragmentation problem solved, no?