[sguav]

Doing VHDL designs for a living here, using SystemVerilog once in a while when absolutely required. Take my words with a good pinch of salt!

SV is anyway a hardware description language, so you still think and code in terms of modules and signals (wires) to be connected. But if you want to create structures that use variables and have a more "procedural" style, I find that SV is more agile than VHDL for this specific purpose.

If you want real high level languages for hardware there are tools that provide synthesis from C/C++, Python and more software oriented languages.

[rbanffy]

> there are tools that provide synthesis from C/C++, Python and more software oriented languages

That sounds extremely interesting!

[imstate]

Beware, its much harder to get the correct hardware design useing these tools.

If that doesn't matter, then go for it!

[rbanffy]

I would imagine that.

A functional language like Haskell would probably be easier to compile to hardware.