[stagger87]

Impressive project. Writing all the VHDL including the FFT and Viterbi decoder... I'm genuinely curious where the ROI on a project like comes from? Selling hardware and training materials? I'm assuming there must have been significant interest from customers, or maybe this is an ambitious employees side project?

Can't wait to see a demo or some pictures of it running.

Would love to see more details about the DSSS demod using the 20MHz rate, specifically regarding the correlation. Any references on this?

(I'm a happy owner of the x115, been looking at the 2.0 for awhile now)

[ChuckMcM]

Oddly enough, some folks like doing this because of the dopamine hit of really understanding how something works. FWIW I'm that kind of person :-). But I certainly understand it isn't for everyone.

The platform I've been using to explore stuff like this is an Ultra96 board with a LimeSDR as the receiver. The Ultra96 has the Zynq Ultrascale FPGA on it. Given that USB3 latency is < 10 uSec I am guessing (hoping?) I can implement it in the Ultrascale fabric which is fed IQ data from the USB 3.1 port.

[TaylorAlexander]

Heh I’m that kind of person too. All my free time is spend building things!

[chris37879]

Yup, I love that feeling, I'm currently working on a software 3d renderer, I've always understood in principle how they work, but getting to actually implement one is really fun.

[rasz]

Afaik USB3 latency is same as USB2, uSOFs every 125us, lowest round trip 2*125us

[csboyer]

For DSSS demod, my guess is a 20 tap match filter designed from a resampled RRC filtered barker sequence. Haven’t looked at the VHDL, but that’s how I’d do it.