[mhh__]

https://en.wikipedia.org/wiki/Transistor_count#MOSFET_nodes

Look it up yourself. Intel being on 14nm vs (say) 5nm is actually quite flattering to Intel.

[SoSoRoCoCo]

That only lists the number, not what the # actually means in terms of actual lithography or more importantly, transitor performance. It used to be minimum feature size, or just L of the gate, but with finfet it can be an overloaded term. Scaling in x of .75 and y of .7 lead to 10% performance improvement per node at Intel. TSMC hasn't been that clear. And that doesn't even account for increase in metal layers, pitch of layers (or if they use poly lower layers to get even faster gains), or average track density due to above/below electromigration minimums.

EDIT: All of this stuff is usually stated at ISSCC every time a new process is announced, so it isn't NDA. I haven't followed this in years which is why I was asking for a process person to step in.

[mhh__]

And what information is there that isn't under NDA?

[brennanpeterson]

Everything in M1 and everything on Intel 14nm. Go read wikichip. It is there. IEDM just happened, tons of detail there.

3nm, sure, good luck.

[brennanpeterson]

Intel 14nm is 42/70/52 (fin/cgp/mmp) with a 7.5 track height. HD stamBitcell is 0.05um2 Very restrictive design rules

Tsmc 5nm is 27/54/36 with a 6T and 7.T option. More open design rules. HD SRAM cell is about 0.025um2.

This is almost exactly what you expect for 1 node of litho scaling.

The more difficult part is that the designs and related process optimizations for intel are different.