[dhanna]

SiFive really didn’t choose chisel as much as created it. It’s basically a company created by Krste and some former graduate students.

I like chisel as a concept but the learning curve is too high: Scala is kind of a mess and when you add a custom DSL + lots of functional programming on top a different hardware design methodology, it becomes overwhelming to your typical ce/ee, who probably doesn’t have that exposure. I simply ran out of time to learn it properly.

It also a second class citizen when it comes to rtl tools. The verification engineers have to work with the generated verilog and it looks like a nightmare. There was some improvements recently but the engineers knowledgeable enough to work on this stuff seem pretty bandwidth constrained.

The biggest headwind to chisel is the breadth of knowledge required to work and improve it IMO.

I’m really hoping that pymtl gets a firrtl backend soon. Python has a pretty decent record for building DSLs.