[FullyFunctional]

Facts:

Chisel is NOT HLS at all. Chisel is one of many languages that generates HDL, that is, you describe code to built a circuit whereas in eg. Verilog you just describe the circuit (Verilog has a limited ability to do dynamically with generate statements).

An HLS is one that raise the abstraction. Almost all of them today allows you to write "lightly" annotated C[++] that gets translated into a circuit. Almost universally, the timing relationship isn't explicit at all.

Opinions:

All existing HDLs and HLSes are terrible and there's fertile ground for creating something to really advance the art. Personally I'm looking for something that is more productive that HDLs, but with more control than an HLS. Some promising examples: Handle C, Google's XLS (assuming promised development), and Silice.