[tverbeure]

I wrote a long blog post about the VexRiscv RISC-V CPU and how its design methodology is radically different than traditional RTL languages.

The VexRiscv is written in SpinalHDL, which is a close relative of Chisel.

The advantage of SpinalHDL/Chisel is that it supports plug and play configurability that’s impossible with languages like SystemVerilog or VHDL.

You can read about it here: https://tomverbeure.github.io/rtl/2018/12/06/The-VexRiscV-CP...

That said: there must be at least 50 open source RISC-V cores out there, and only a small fraction is written in Chisel. I don’t see how the use of Chisel has held back RISC-V in any meaningful way.