[unionpivo]

Please note I am software dev, not a hardware guy, and I just got my first FPGA during holidays, and am just beginning to play with it.

> There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1].

I don't understand what is embarrassing about the answer ? As a software guy above answer make sense. Some problems you want to use C (or similar) for and some problems you want to use scripting language for, and then again sometimes the right tool is erlang, rust or go-lang ...

But like I said, that's my software guy perspective, so I am wondering what I missed?

[alain94040]

I just read the answer as well. It's not "embarrassing", but it basically doesn't answer the question. Instead, it argues that the question is equivalent to asking what's the point of Python vs. C.

So in the end, the answer doesn't provide any specific answer regarding SystemVerilog and Chisel. All I found is one mention of negotiating parameters, which Verilog doesn't do. I would have loved to hear a lot more about examples of what Chisel makes more convenient than SystemVerilog.