[leecb]

Everything described in the article sounds exactly like some of the Virtex*-FX products from more than 10 years ago.

For instance, the Virtex4-FX had either one or two 450MHz PowerPC coresembedded in it, where you could implement 8 of your own additional instructions in the FPGA. This is effectively now a CPU where you can extend the instruction set, and design your own instructions specific to your application. For example, you might make special instructions using the onboard logic to accelerate video compression, or math operations; I know of one application that was designed to do a 4x4 matrix multiply per cycle.

https://www.digikey.com/catalog/en/partgroup/virtex-4-fx-ser... https://www.xilinx.com/support/documentation/data_sheets/ds1...

[thrtythreeforty]

For those curious, Xtensa is a similar embeddable architecture (known especially for its use in the ESP32 microcontroller) that allows broad latitude to the designer to customize its instruction set with custom acceleration. The integration is very good, the compiler recognizes the new intrinsics and the designer has control over how the instruction is pipelined into the main processor.

Unfortunately it's very proprietary, and as far as I know there isn't an at-home version you can play with on FPGAs. But this kind of thing does exist if you can afford it - you don't have to roll your own RTL.

[jng]

I am very familiar with the new Zynq family, embedding ARM cores on the same die together with FPGA fabric. I didn't know that the PowerPC version allowed such a tight coupling as handing off an instruction to programmable logic, the current Zynq models are much more lightly coupled, using AXI buses to connect the ARM cores with the PL (and many other components on the same SoC).

[mhh__]

What was the latency like to actually get data into your shiny new instruction e.g. do I get a 14 stage pipeline stall to actually use the instruction?

[rowanG077]

That depends on how you designed your instruction.

[sitkack]

And your pipeline