I actually think there's a pretty easy way around this for Google. They could create a ARM -> RISC-V translation layer. That works well because RISC-V already has a very limited instruction set. In order to make things fast, you don't need to do a lot of fancy transforms.
The issue with doing the same ARM->x86 translation is the x86 instruction set is vast and to get the best performance requires you effectively use those instructions. That requires you to merge instructions that you wouldn't have merged (think of things like the lea instruction).
There's less of an instruction impedance mismatch going from ARM to RISC-V.
Interestingly, I think going from x86->ARM or RISC-V would present less of a performance problem. That's because most of the work would be splitting one instruction into many. The evidence of this is the x86->IA-64 which resulted in something like a 10->20% performance loss vs a natively compiled IA-64.
The issue with doing the same ARM->x86 translation is the x86 instruction set is vast and to get the best performance requires you effectively use those instructions. That requires you to merge instructions that you wouldn't have merged (think of things like the lea instruction).
There's less of an instruction impedance mismatch going from ARM to RISC-V.
Interestingly, I think going from x86->ARM or RISC-V would present less of a performance problem. That's because most of the work would be splitting one instruction into many. The evidence of this is the x86->IA-64 which resulted in something like a 10->20% performance loss vs a natively compiled IA-64.