[raghavtoshniwal]

The tradeoff is to keep design complexity as low as possible while carving out sections of the chip for specialized tasks. Apple’s new M1 chip has a ‘neural processor’ that works with Tensorflow to provide a speedup. They thought it was worth the added complexity. They also have 4 low power cores for background tasks.

Alot of DSP and networking tasks are handled by the modem itself.

Software and Compiler toolchains are often quick to optimize for any improvements that a processor provides but the bottleneck generally is cost and complexity which don’t scale linearly.