| Nicely written article. A few minor nits: * As such, the development lifecycle is incredibly long. It starts with prototyping in an FPGA (Field Programmable Gate Array), in which chip designers can program their required functionality and confirm compatibility* I’ve been involved with development of multiple generations of ASICs including 7nm and now 5nm. Going all the way back to 40nm, we never prototyped in FPGAs. Most designs will not fit into a single FPGA and designs involving multiple FPGAs are a headache and the design diverges rapidly from your target due to all the overhead associated with coordinating multiple FPGAs. Prototype might be something you do for a very simple design and a new or inexperienced team. If you have a good experienced team, the tooling is good enough that simulation and verification are all that’s needed. However verification is a very extensive process and the most time consuming part and can take 9-12 months. 7nm tape-outs are extremely expensive. So you want to get it right. Most designs have multiple options built in on risky sections so that a work-around for a bug can be done in a metal spin. Furthermore, most of these chips have significant FW/SW associated with them as well. If you think about it, that’s quite a lot to deliver in 2 years into something as reliable as a network processor. When you consider all of the above, Broadcom does an amazing job going from TH3 to TH4 in only 2 years. They are tough to beat because they have such a good process that they can crank out these incredibly complex chips on a reliable cadence. Please note that this includes analog for the SERDES which is its own development. |
It definitely depends on what you're building. When I worked on GPUs at Broadcom and CPUs at arm (and now working on OpenTitan: https://opentitan.org/) FPGAs were used. At both companies you could create a sufficiently small configuration of the design that a single FPGA was a viable target without requiring heroics for coordinating multiple FPGAs (For the GPU turn down the number of cores, for CPU I was working on the little designs A55 and such which you could fit in a sufficiently large FPGA).
Though I'd agree FPGAs aren't often used a prototyping tool. They're used for verification and often once the design is fairly mature (they're inevitably a pain to setup and use so you want to iron out all the stupid bugs first, FPGAs are most useful when you need to be running many cycles to find an issue).